The present invention relates to a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals.
Conventionally, there have been proposed various techniques concerning a ΔΣ (delta sigma)-type A/D converter. For example, Japanese Unexamined Patent Publication No. Hei 6(1994)-120837 describes a technique for controlling a zero point in quantization noise shape with accuracy without having to consider the minimum size of the use process. Further, Japanese Unexamined Patent Publication No. 2003-163596 describes a technique for suppressing the adverse effect of an idle tone which occurs in a ΔΣ-type A/D converter by using a DC dither signal (DC addition voltage). The idle tone refers to a periodic noise signal which occurs by a feedback loop and an integrating circuit in the ΔΣ-type A/D converter in the case of no analog input signal or a minute analog input signal to the ΔΣ-type A/D converter. The idle tone is described in detail, for example, in “An Introduction to ΔΣ-type analog/digital converters” written by Richard Schreier, Gabor C. Temes, translated by Takao Waho and Akira Yasuda, published by Maruzen Co., Ltd. on Oct. 10, 2007, pp. 34-37.